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Application Note 9910
WARNING: Ensure care is utilized to prevent the
application of reverse polarity power to the CCA.
7. Connect the supplied ribbon cable from the PC’s parallel
port to the evaluation board’s J10 connector ensuring the
arrow indicating pin one on the ribbon cable connector J1
and the CCA J10-1 are correctly mated.
Software Description
The evaluation software provides a graphical user interface
that allows full control over the ISL5217 evaluation board.
Through the software, all operational modes of the ISL5217
can be exerted, via the FPGA and SRAM. The software also
implements functions for loading stimulus patterns into
external memory, loading coefficient files for the internal FIR
filters, and loading gain profiles for the internal Gain Control.
The software supports user firmware development by
copying device RAM coefficients into *.hex files while
loading. This provides the user with the ability to quickly
review coefficient address allocation within the device.
Controlling the board can be done by using the forms
provided in the software, by using the active command
window to execute commands pertaining to accessing
registers directly in a peek/poke manner, or by running
scripts. The software contains eight forms, each controlling a
specific part of the board. For example, the inputs form
controls the data input mode, the time slot counters, the
serial word length, and serial modes for the device. The
software has pull-down menus through which the user can
execute various commands. These commands include
running scripts, recording macros, issuing resets, …etc.
These functions are discussed in more details in the
following sections. The software also support the control of
up to four ISL5217 boards simultaneously, through selection
of the Brd0-Brd3 indicator buttons.
NOTE: Utilize care to ensure that the Brd1-Brd3 controls
are not accessed when these boards are not present.
The software will require the selection of Actions, FPGA
Hard Reset, in the event of access to unconnected
boards.
Running the Software
1. Turn on the power supply.
2. Execute ‘PUC.exe’.
3. Select ‘File’ then ‘Load Configuration’.
4. Select the desired configuration file, then select OK.
5. The ‘PUC.exe’ active window will display the execution
results of the selected configuration and the evaluation
CCA will be operational.
Controlling the ISL5217
Software Forms
The software provides six different forms for controlling the
ISL5217 device, one form for controlling the evaluation CCA,
and one form controlling the factory test modes of the
3
ISL5217 device. These forms can set or clear various
register bits, and load associated memories. For more
information concerning the interpretations of the bit fields
inside these forms, refer to the ISL5217 data sheet.
Switching between forms can be done using the Tab toolbar.
A brief discussion of the software forms follows:
Many of the forms contain Channel 0-Channel 3, write to all
channels, Immediate Update, and Software Update buttons.
These selections are shared by multiple tabs and allow the
user to select single or all channel broadcasts and the
update control. Only the indicator button shown in red will be
the active button. All settings displayed, including filter and
pattern file names, on each tab conform to only the active
channel. All updates will be performed in accordance with
the selected, red, update mode.
The active command line window reflects the commands
being implemented by the PUC program. From this window
you can observe which device and FPGA registers are being
updated based on the graphical interface changes. Please
see the Command Line Window section for additional
details.
Inputs: This form controls the input data settings. The Data
Input source, FIFO Almost Empty Threshold, SCLK Mode,
SCLK Divider, I and Q time slot counter settings, SData
Source, Serial word length, TxEnable, Update, Software
TxEnable, FSRB, and serial channel polarities.
DataFlow1: This form controls the symbol rate, Fixed
Integer Divider settings, Epoch Frame strobe, Phase Offset,
Sample phase clear, half course sample delay, FIR inputs
on, the shaping filter bank and coefficients contents, the
modulation type, the number of interpolation phases, and the
data span. Contents of the coefficient RAMs can be changed
by specifying a file and selecting symmetric and the load
both options. As described in the device data sheet, it is
possible to load two FIR coefficient files and to switch
between the separate banks. Symmetric should be selected
when the filter file contains only 1/2 of the coefficients
required. When selected, the filter coefficients are processed
and loaded to provide for a full filter span. The files displayed
and actions executed only pertain to the channel selected.
To see the contents of other channel FIR memories and load
or update them, you must change the channel selector or
select write to all channels.
DataFlow2: This form controls the Carrier phase and
frequency, with space reserved for gain profile loading as
this feature becomes available.
Outputs: This form controls Channel enable, gain multiplier,
step attenuation, output channel routing to summers,
cascade enable, cascade delay, istrobe enable and polarity,
SYNCO polarity, output enable, and output mode.
Control: This form controls the update mask, uP access to
the device RAMS, and device soft reset.
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